1. Field of the Invention
The present invention relates to a neuro computer and more particularly to a neuro computer realized by connecting an analog neuron chip through an analog time divisional transmission path.
2. Description of the Related Art
In a conventional sequential processing computer (Von Neumann type) it is difficult to control a data process function in accordance with a variation in the usage method or environment. Therefore, an adaptive data processing method utilizing a parallel distribution system and a layered network is proposed. The back propagation method (D. E. Rumelhart, G. E. Hinton, and R. J. Williams, "Learning Internal Representations by Error Propagation", PARALLEL DISTRIBUTED PROCESSING, Vol. 1, pp. 318-364, The MIT Press, 1986) receives particular attention because of its high practicality.
The back propagation method utilizes a layered structure network comprising a node called a basic unit and internal connection having weights presented. FIG. 1 shows the structure of a basic unit 1. Basic unit 1 carries out a process similar to a continuous neuron model. It comprises a multiple-input single-output system and further comprises a multiplication unit 2 for multiplying a plurality of inputs (Y.sub.h) by respective weights (W.sub.ih) of the internal connections, an accumulating unit 3 for adding all the multiplied results, and a threshold value processing unit 4 for outputting a final output X.sub.i by applying a nonlinear threshold value process to the added values.
FIG. 2 shows a conceptual view of the structure of a layered neural network. Many basic units (1-h, 1-i, 1-j) are connected in layers as shown in FIG. 2 and the output signal patterns corresponding to the input signal patterns are outputted.
Upon learning, the weights (W.sub.ih) of connections between respective layers are determined in order to minimize the difference between the output patterns and a target teacher pattern. This learning is applied to a plurality of input patterns and then multiplexed. Upon an association operation, even if the input pattern contains information which is slightly incomplete upon the learning and therefore different from the complete information input upon the learning, an output pattern close to the teacher pattern produced during the learning process is generated, thereby enabling a so-called associating process.
To realize a neuron computer with such a structure, transmission and reception of the data between basic units constituting a layered network is conducted by as small a number of wires as possible. This is a problem which needs to be solved when a complex data process is realized by forming multilayers of the network structure and increasing the number of basic units.
However, the data transmission system explained above requires a large number of wires between the two layers, thus preventing it from being made small. Further, its reliability cannot be increased when the layered network is manufactured into a chip. For example, consider a complete connection in which the number of adjacent layers is made the same and all the basic units 1 are connected to each other. In this case, the number of the wires increases in proportion to the second power of the number of basic units, thereby resulting in a rapid increase in the number of wires.